The invention relates to multiple stage delta sigma modulators.
Fractional-N synthesizers have many advantages over their conventional counterparts, integer N synthesizers. These include, among others, high frequency resolution, fast channel switching speed, low in-band phase noise, less stringent phase noise requirement on the external VCOs, permitting direct digital modulation.
One way of achieving non-integer multiplication of the reference frequency is through switching the division ratio of the divider among different integers so that the xe2x80x9caveragexe2x80x9d divider output cycle seen by the phase frequency detector is a non-integer multiple of the VCO period. However, the dithering of the rising edge of the divider output, as a result of the switching action, could cause unacceptably high phase noise and sidebands within the loop bandwidth if a simple bit stream generator is employed. Because of this, high order delta sigma modulators capable of shifting low frequency noise into high frequencies are required. The shifted low frequency noise will be subsequently filtered out by the low pass response of the loop.
Unfortunately, such high resolution multi-bit delta sigma modulators consume chip area and power. This leads to a higher cost for integrated circuits and either increases the battery size of portable equipment containing these devices or reduces battery life.
As a rule of thumb, the amount of hardware in a digital delta sigma modulator is roughly proportional to the order of the delta sigma modulator resolution of the delta Sigma modulator. High order modulators are desirable since they provide better noise shaping to reduce the baseband quantization noise. Lower quantization noise Is often necessary to meet phase noise requirements of transmitters or receivers. High resolution is also desirable since this allows very low step size at the synthesizer output. This low step size can be useful for trimming the radio either in production or in the field. Both these desirable features (resolution and order) come at the expense of an increase amount of digital hardware.
To further explain the problem, a 10 bit, fourth order delta sigma modulator of the MASH 1-1-1-1 type requires four 10 bit accumulators along with a smaller amount of logic to implement the Pascals Triangle configuration. Wells, in U.S. Pat. No. 4,609,881 discloses such a modulator. Thus, if we take four 10 bit accumulators as equivalent to 40 single bit accumulators (SBA), the Wells design requires 40 SBA""s along with the logic required for the above triangle.
Other delta sigma modulator architectures (such a disclosed by Gaskel in U.S. Pat. No. 5,079,521) have overhead as well. For example, delta sigma modulator architectures composed of cascaded second or higher order stages have a recombination network similar in complexity and size to the Pascals Triangle recombination network.
Another source of overhead arises in second or higher order delta sigma modulators. Here, the number of bits in each accumulator must be larger than the resolution required. As an example, FIG. 10 of U.S. Pat. No. 5,053,802 issued to Heitala shows two 27 bit accumulators for a 24 bit, second order delta sigma modulator. Thus, we would call the 3 bit adder and 6 extra SBA""s (3 extra SBA""s per accumulator) overhead.
This overhead can be even higher if we wish to accommodate a wide range of synthesizable frequencies. Again, an example can be shown with reference to FIG. 10 in Heitala. The amount of overhead required depends on the input to the delta sigma modulator. When the input is close to the maximum value that can be accommodated in a 24 bit bus, either the number of bits in the feedback logic, or the number of bits in the accumulators has to increase beyond the minimum that is required when the input is close to a value in the middle of the input range.
If reduced digital hardware was required, either the resolution or the order of any given delta sigma modulator architecture had to be reduced.
What is therefore required is a delta sigma modulator which allows a reduction of both overhead hardware and an escape from the traditional constraints on the number of single bit accumulators. Such a modulator would occupy less chip area and reduce power consumption allowing longer battery life or smaller batteries.
The present invention overcomes the shortcomings of the prior art by providing a method and a delta sigma modulator which uses at least one quantizer having a dead zone. The dead zone quantizer outputs a zero when its input is within the dead zone range. It outputs a predetermined value if the input is above the dead zone range. If the input is below the dead zone range, the quantizer outputs another predetermined value. Ideally, the quantizer dead zone thresholds are complimentary in that the upper threshold for an input is the positive value of the lower threshold.
Also, to save on accumulator bits, the delta sigma modulator selects a predetermined number of most significant bits at different stages.
In one embodiment, the present invention provides a multiple stage delta sigma modulator comprising, a primary first order delta sigma modulator coupled to receive an input and producing an intermediate output which is a quantization of the input and a residue output which is a quantization noise signal, a secondary delta sigma modulator coupled to receive the residue output and producing a secondary output which is a quantization of the residue output and a recombiner coupled to receive the intermediate output and the secondary output and producing a final output, wherein the secondary delta sigma modulator has an order of at least 2.
In another embodiment, the present invention provides a method of reducing components in a delta sigma modulator having multiple stages, said modulator having at least one quantizer, the method comprising quantizing an input signal by selecting a predetermined number of most significant bits in an input signal as a quantizer output.
In yet another embodiment, the invention provides a delta-sigma modulator including a first accumulator, a second accumulator, and a truncation stage coupled between the first accumulator and the second accumulator wherein the truncation stage receives a digital output of the first accumulator, the truncation stage transmits a digital truncation output to the second accumulator, the truncation stage truncates the digital output of the first accumulator to produce the truncation output, and the digital output of the first accumulator has more digits than the truncation output.
Another embodiment of the invention provides a delta-sigma modulator including a quantizer, calculation means to calculate an amount of quantization error introduced by the quantizer such that the quantization error is represented by a digital number, and truncation means to truncate the digital number representing the quantization error wherein the quantizer is coupled to the calculation means and the truncation means is coupled to the calculation means.